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? 2004 microchip technology inc. ds21810d-page 1 mcp6271/2/3/4/5 features ? gain bandwidth product: 2 mhz (typ.) supply current: i q = 170 a (typ.) supply voltage: 2.0v to 5.5v rail-to-rail input/output extended temperature range: -40c to +125c available in single, dual and quad packages single with chip select (cs ) ( mcp6273 ) dual with chip select (cs ) ( MCP6275 ) applications automotive portable equipment photodiode amplifier analog filters notebooks and pdas battery-powered systems available tools spice macro model (at www.microchip.com) filterlab ? software (at www.microchip.com) description the microchip technology inc. mcp6271/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. this family has a 2 mhz gain bandwidth product (gbwp) and a 65 phase margin. this family also operates from a single supply voltage as low as 2.0v, while drawing 170 a (typ.) quiescent current. additionally, the mcp6271/2/3/4/5 supports rail-to-rail input and output swing, with a common mode input voltage range of v dd +300mv to v ss ? 300 mv. this family of operational amplifiers is designed with microchip?s advanced cmos process. the MCP6275 has a chip select input (cs ) for dual op amps in an 8-pin package and is manufactured by cascading two op amps (the output of op amp a connected to the non-inverting input of op amp b). the cs input puts the device in low-power mode. the mcp6271/2/3/4/5 family operates over the extended temperature range of -40c to +125c, with a power supply range of 2.0v to 5.5v. package types 4 5 v in _ mcp6271 v dd 1 2 3 4 8 7 6 5 - + nc nc nc v in + v ss mcp6272 pdip, soic, msop mcp6274 1 2 3 4 14 13 12 11 - + - + 10 9 8 5 6 7 + - - + pdip, soic, tssop 1 2 3 4 8 7 6 5 - + - + v out mcp6273 1 2 3 4 8 7 6 5 - + v ina _ v ina + v ss v outa v outb v dd v inb _ v inb + v ss v in + v in _ nc cs v dd v out nc v outa v ina _ v ina + v dd v ss v outb v inb _ v inb + v outc v inc _ v inc + v outd v ind _ v ind + pdip, soic, msop pdip, soic, msop MCP6275 pdip, soic, msop 1 2 3 4 8 7 6 5 + - v ina _ v ina + v ss v outa /v inb + v outb v dd v inb _ cs -+ mcp6271 sot-23-5 4 1 2 3 - + 5 v dd v in ? v out v ss v in + mcp6271r sot-23-5 1 2 3 - + v ss v in ? v out v dd v in + mcp6273 sot-23-6 4 1 2 3 - + 6 5 v ss v in + v out cs v dd v in _ 170 a, 2 mhz rail-to-rail op amp
mcp6271/2/3/4/5 ds21810d-page 2 ? 2004 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ? v ss ........................................................................7.0v all inputs and outputs ................... v ss ? 0.3v to v dd + 0.3v difference input voltage ...................................... |v dd ? v ss | output short circuit current .................................continuous current at input pins ....................................................2 ma current at output and supply pins ............................30 ma storage temperature.....................................-65c to +150c junction temperature (t j ) . .........................................+150c esd protection on all pins (hbm/mm) ................ 4 kv/400v ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this sp ecification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc electrical specifications electrical characteristics : unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm = v dd /2, r l = 10 k ? to v dd /2 and v out v dd /2. parameters sym min typ max units conditions input offset input offset voltage v os -3.0 ? +3.0 mv v cm = v ss (note 1) input offset voltage (extended temperature) v os -5.0 ? +5.0 mv t a = -40c to +125c, v cm = v ss (note 1) input offset temperature drift ? v os / ? t a ?1.7?v/ct a = -40c to +125c, v cm = v ss (note 1) power supply rejection ratio psrr 70 90 ? db v cm = v ss (note 1) input bias current and impedance input bias current i b ? 1.0 ? pa note 2 at temperature i b ? 50 200 pa t a = +85c (note 2) at temperature i b ?2 5nat a = +125c (note 2) input offset current i os ? 1.0 ? pa note 3 common mode input impedance z cm ?10 13 ||6 ? ? ||pf note 3 differential input impedance z diff ?10 13 ||3 ? ? ||pf note 3 common mode (note 4) common mode input range v cmr v ss ? 0.3 ? v dd +0.3 v note 4 common mode rejection ratio cmrr 70 85 ? db v cm = -0.3v to 2.5v, v dd = 5v common mode rejection ratio cmrr 65 80 ? db v cm = -0.3v to 5.3v, v dd = 5v open-loop gain dc open-loop gain (large signal) a ol 90 110 ? db v out = 0.2v to v dd ? 0.2v, v cm =v ss, (note 1) output maximum output voltage swing v ol , v oh v ss +15 ? v dd ? 15 mv output short-circuit current i sc ?25?ma power supply supply voltage v dd 2.0 ? 5.5 v quiescent current per amplifier i q 100 170 240 a i o = 0 note 1: the MCP6275?s v cm for op amp b (pins v outa /v inb + and v inb ?) is v ss + 100 mv. 2: the current at the MCP6275?s v inb ? pin is specified by i b only. 3: this specification does not apply to the MCP6275?s v outa /v inb + pin. 4: the MCP6275?s v inb ? pin (op amp b) has a common mode range (v cmr ) of v ss + 100 mv to v dd ? 100 mv. the MCP6275?s v outa /v inb + pin (op amp b) has a voltage range specified by v oh and v ol .
? 2004 microchip technology inc. ds21810d-page 3 mcp6271/2/3/4/5 ac electrical specifications temperature specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 10 k ? to v dd /2 and c l = 60 pf. parameters sym min typ max units conditions ac response gain bandwidth product gbwp ? 2.0 ? mhz phase margin at unity-gain pm ? 65 ? slew rate sr ? 0.9 ? v/s noise input noise voltage e ni ? 3.5 ? v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ? 20 ? nv/ hz f = 1 khz input noise current density i ni ? 3?fa/ hz f = 1 khz electrical characteristics: unless otherwise indicated, v dd = +2.0v to +5.5v and v ss = gnd. parameters sym min typ max units conditions temperature ranges operating temperature range t a -40 ? +125 c note storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot-23 ja ?256?c/w thermal resistance, 6l-sot-23 ja ?230?c/w thermal resistance, 8l-pdip ja ?85?c/w thermal resistance, 8l-soic ja ?163?c/w thermal resistance, 8l-msop ja ?206?c/w thermal resistance, 14l-pdip ja ? 70 ? c/w thermal resistance, 14l-soic ja ? 120 ? c/w thermal resistance, 14l-tssop ja ? 100 ? c/w note: the junction temperature (t j ) must not exceed the absolute maximum specification of +150c.
mcp6271/2/3/4/5 ds21810d-page 4 ? 2004 microchip technology inc. mcp6273/MCP6275 chip select (cs ) specifications figure 1-1: timing diagram for the c hip select (cs ) pin on the mcp6273 and MCP6275. electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 10 k ? to v dd /2 and c l = 60 pf. parameters sym min typ max units conditions cs low specifications cs logic threshold, low v il v ss ?0.2v dd v cs input current, low i csl ?0.01? acs = v ss cs high specifications cs logic threshold, high v ih 0.8v dd ?v dd v cs input current, high i csh ?0.7 2 acs = v dd gnd current per amplifier i ss ?-0.7? acs = v dd amplifier output leakage ? ? 0.01 ? a cs = v dd dynamic specifications (note 1) cs low to valid amplifier output, turn-on time t on ?410scs low 0.2 v dd , g = +1 v/v, v in = v dd /2, v out = 0.9 v dd /2, v dd = 5.0v cs high to amplifier output high-z t off ?0.01? scs high 0.8 v dd , g = +1 v/v, v in = v dd /2, v out = 0.1 v dd /2 hysteresis v hyst ?0.6? vv dd = 5v note 1: the input condition (v in ) specified applies to both op amp a and b of the MCP6275. the dynamic specification is tested at the output of op amp b (v outb ). v il hi-z t on v ih cs t off v out -0.7 a (typ.) hi-z i ss i cs 0.7 a (typ.) 0.7 a (typ.) -0.7 a (typ .) -170 a (typ.) 10 na (typ.)
? 2004 microchip technology inc. ds21810d-page 5 mcp6271/2/3/4/5 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 10 k ? to v dd /2 and c l = 60 pf. figure 2-1: input offset voltage. figure 2-2: input bias current at t a = +85c. figure 2-3: input offset voltage vs. common mode input voltage at v dd = 2.0v. figure 2-4: input offset voltage drift. figure 2-5: input bias current at t a = +125c. figure 2-6: input offset voltage vs. common mode input voltage at v dd = 5.5v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% -3.0 -2.4 -1.8 -1.2 -0.6 0.0 0.6 1.2 1.8 2.4 3.0 input offset voltage (mv) percentage of occurrences 832 samples v cm = v ss 0% 4% 8% 12% 16% 20% 24% 28% 32% 0 102030405060708090100 input bias current (pa) percentage of occurrences 422 samples t a = +85c -100 -50 0 50 100 150 200 250 300 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 common mode input voltage (v) input offset voltage (v) v dd = 2.0v t a = +125c t a = +85c t a = +25c t a = -40c 0% 2% 4% 6% 8% 10% 12% 14% -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 input offset voltage drift (v/c) percentage of occurrences 832 samples v cm = v ss t a = -40c to +125c 0% 4% 8% 12% 16% 20% 24% 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 input bias current (na) percentage of occurrences 422 samples t a = +125c -100 -50 0 50 100 150 200 250 300 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input offset voltage (v) v dd = 5.5v t a = +125c t a = +85c t a = +25c t a = -40c
mcp6271/2/3/4/5 ds21810d-page 6 ? 2004 microchip technology inc. typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 10 k ? to v dd /2 and c l = 60 pf. figure 2-7: input offset voltage vs. output voltage. figure 2-8: cmrr, psrr vs. frequency. figure 2-9: input bias, offset currents vs. common mode input voltage at t a =+85c. figure 2-10: input bias, input offset currents vs. ambient temperature. figure 2-11: cmrr, psrr vs. ambient temperature. figure 2-12: input bias, offset currents vs. common mode input voltage at t a = +125c. -100 -50 0 50 100 150 200 250 300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) input offset voltage (v) v dd = 2.0v v cm = v ss representative part v dd = 5.5v 20 30 40 50 60 70 80 90 100 110 1 .e+00 1.e+01 1 .e+02 1.e+03 1 .e+04 1.e+05 1 .e+06 frequency (hz) cmrr, psrr (db) 1 10k 100k 1m 100 10 1k psrr+ psrr- cmrr -25 -15 -5 5 15 25 35 45 55 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias, offset currents (pa) t a = +85c v dd = 5.5v input bias current input offset current 1 10 100 1,000 10,000 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) input bias, offset currents (pa) input bias current input offset current v cm = v dd v dd = 5.5v 60 70 80 90 100 110 120 -50-25 0 25507510012 5 ambient temperature (c) psrr, cmrr (db) psrr v cm = v ss cmrr -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.00.51.01.52.02.53.03.54.04.55.05.5 common mode input voltage (v) input bias, offset currents (na) t a = +125c v dd = 5.5v input bias current input offset current
? 2004 microchip technology inc. ds21810d-page 7 mcp6271/2/3/4/5 typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 10 k ? to v dd /2 and c l = 60 pf. figure 2-13: quiescent current vs. power supply voltage. figure 2-14: open-loop gain, phase vs. frequency. figure 2-15: maximum output voltage swing vs. frequency. figure 2-16: output voltage headroom vs. output current magnitude. figure 2-17: gain bandwidth product, phase margin vs. ambient temperature. figure 2-18: slew rate vs. ambient temperature. 0 50 100 150 200 250 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) quiescent current (a/amplifier) t a = +125c t a = +85c t a = +25c t a = -40c -20 0 20 40 60 80 100 120 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 frequency (hz) open-loop gain (db) -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () gain phase 0.1 1 10 100 1k 10k 100k 1m 10m 100m 0.1 1 10 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) maximum output voltage swing (v p-p ) v dd = 2.0v 1k 10k 100k 1m v dd = 5.5v 10m 1 10 100 1000 0.01 0.1 1 10 output current magnitude (ma) ouput voltage headroom (mv) v ol - v ss v dd - v oh 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -50 -25 0 25 50 75 100 125 ambient temperature (c) gain bandwidth product (mhz) 50 55 60 65 70 75 80 phase margin () gain bandwidth product v dd = 5.5v v dd = 2.0v v dd = 2.0v v dd = 5.5v phase margin 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) rising edge, v dd = 2.0v rising edge, v dd = 5.5v falling edge, v dd = 2.0v falling edge, v dd = 5.5v
mcp6271/2/3/4/5 ds21810d-page 8 ? 2004 microchip technology inc. typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 10 k ? to v dd /2 and c l = 60 pf. figure 2-19: input noise voltage density vs. frequency. figure 2-20: output short-circuit current vs. power supply voltage. figure 2-21: quiescent current vs. chip s elect (cs ) voltage at v dd = 2.0v (mcp6273 and MCP6275 only). figure 2-22: input noise voltage density vs. common mode input voltage at 1 khz. figure 2-23: channel-to-channel separation vs. frequency (mcp6272 and mcp6274). figure 2-24: quiescent current vs. chip s elect (cs ) voltage at v dd = 5.5v (mcp6273 and MCP6275 only). 10 100 1,000 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) input noise voltage density (nv/ ? hz) 0.1 100 10 1k 100k 10k 1m 1 0 5 10 15 20 25 30 35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) ouptut short circuit current (ma) t a = +125c t a = +85c t a = +25c t a = -40c 0 50 100 150 200 250 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 chip select voltage (v) quiescent current (a/amplifier) hysteresis op-amp shuts off here op-amp turns on here v dd = 2.0 v cs swept high to low cs swept low to high 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common mode input voltage (v) input noise voltage density (nv/ hz) f = 1 khz v dd = 5.0v 100 110 120 130 140 1 10 100 frequency (khz) channel-to-channel separation (db) 0 100 200 300 400 500 600 700 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 chip select voltage (v) quiescent current (a/amplifier) hysteresis op amp toggles on/off here v dd = 5.5v cs swept low to high cs swept high to low
? 2004 microchip technology inc. ds21810d-page 9 mcp6271/2/3/4/5 typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v dd = +2.0v to +5.5v, v ss = gnd, v cm = v dd /2, v out v dd /2, r l = 10 k ? to v dd /2 and c l = 60 pf. figure 2-25: large-signal non-inverting pulse response. figure 2-26: small-signal non-inverting pulse response. figure 2-27: c hip select (cs ) to amplifier output response time at v dd = 2.0v (mcp6273 and MCP6275 only). figure 2-28: large-signal inverting pulse response. figure 2-29: small-signal inverting pulse response. figure 2-30: c hip select (cs ) to amplifier output response time at v dd = 5.5v (mcp6273 and MCP6275 only). 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -5 0 5 1 0 15 20 25 30 35 40 45 time (5 s/div) output voltage (v) g = +1v/v v dd = 5.0v time (2 s/div) output voltage (10 mv/div) g = +1v/v 0.0 0.5 1.0 1.5 2.0 2.5 -5. 0 0 .0 5. 0 10 .0 15 .0 2 0.0 2 5.0 3 0.0 35 .0 40. 0 45. 0 time (5 s/div) chip select, output voltages (v) v out output on output high-z v dd = 2.0v g = +1v/v v in = v ss cs voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -5 0 5 10 15 20 25 30 3 5 40 45 time (5 s/div) output voltage (v) g = -1v/v v dd = 5.0v time (2 s/div) output voltage (10 mv/div) g = -1v/v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -5 0 5 1 0 15 20 25 3 0 35 40 45 time (5 s/div) chip select, output voltages (v) v out output on output high-z v dd = 5.5v g = +1v/v v in = v ss cs voltage
mcp6271/2/3/4/5 ds21810d-page 10 ? 2004 microchip technology inc. 3.0 pin descriptions descriptions of the pins are listed in table 3-1 (single op amps) and table 3-2 (dual and quad op amps). table 3-1: pin function table for single op amps table 3-2: pin function table for dual and quad op amps. 3.1 analog outputs the output pins are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs are high- impedance cmos inputs with low bias currents. 3.3 MCP6275?s v outa /v inb + pin for the MCP6275 only, the output of op amp a is connected directly to the non-inverting input of op amp b; this is the v outa /v inb + pin. this connection makes it possible to provide a cs pin for duals in 8-pin packages. 3.4 cs digital input this is a cmos, schmitt-triggered input that places the part into a low-power mode of operation. 3.5 power supply (v ss and v dd ) the positive power supply (v dd ) is 2.0v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need a local bypass capacitor (typically 0.01 f to 0.1 f) within 2 mm of the v dd pin. these parts need to use a bulk capacitor (within 100 mm), which can be shared with nearby analog parts. mcp6271 (pdip, soic, msop) mcp6271 (sot-23-5) mcp6271r (sot-23-5) mcp6273 (pdip, soic, msop) mcp6273 (sot-23-6) symbol description 61161v out analog output 24424v in ? inverting input 33333v in + non-inverting input 75276v dd positive power supply 42542v ss negative power supply ???85cs chip select 1,5,8 ? ? 1,5 ? nc no internal connection mcp6272 mcp6274 MCP6275 symbol description 11?v outa analog output (op amp a) 222 v ina ? inverting input (op amp a) 333 v ina + non-inverting input (op amp a) 848 v dd positive power supply 55?v inb + non-inverting input (op amp b) 666 v inb ? inverting input (op amp b) 777v outb analog output (op amp b) ?8?v outc analog output (op amp c) ?9? v inc ? inverting input (op amp c) ?10? v inc + non-inverting input (op amp c) 4114 v ss negative power supply ?12? v ind + non-inverting input (op amp d) ?13? v ind ? inverting input (op amp d) ?14? v outd analog output (op amp d) ?? 1v outa /v inb + analog output (op amp a)/non-inverting input (op amp b) ?? 5 cs chip select
? 2004 microchip technology inc. ds21810d-page 11 mcp6271/2/3/4/5 4.0 application information the mcp6271/2/3/4/5 family of op amps is manufac- tured using microchip?s state-of-the-art cmos process, specifically designed for low-cost, low-power and general purpose applications. the low supply voltage, low quiescent current and wide bandwidth makes the mcp6271/2/3/4/5 ideal for battery-powered applications. 4.1 rail-to-rail inputs the mcp6271/2/3/4/5 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. figure 4-1 shows the input voltage exceeding the supply voltage without any phase reversal. figure 4-1: the mcp6271/2/3/4/5 show no phase reversal. the input stage of the mcp6271/2/3/4/5 op amps use two differential cmos input stages in parallel. one operates at low common mode input voltage (v cm ) and the other at high v cm . with this topology, the device operates with v cm up to 0.3v above v dd and 0.3v below v ss . the input offset voltage (v os ) is measured at v cm =v ss ? 0.3v and v dd + 0.3v to ensure proper operation. input voltages that exceed the absolute maximum volt- age (v ss ?0.3v to v dd + 0.3v) can cause excessive current to flow into or out of the input pins. current beyond 2 ma can cause reliability problems. applications that exceed this rating must be externally limited with a resistor, as shown in figure 4-2. figure 4-2: input current limiting resistor (r in ). 4.2 rail-to-rail output the output voltage range of the mcp6271/2/3/4/5 op amps is v dd ?15mv (min.) and v ss +15mv (max.) when r l =10k ? is connected to v dd /2 and v dd = 5.5v. refer to figure 2-16 for more information. 4.3 capacitive loads driving large capacitive loads can cause stability problems for voltage-feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. a unity-gain buffer (g = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 100 pf when g = +1), a small series resistor at the output (r iso in figure 4-3) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-3: output resistor, r iso stabilizes large capacitive loads. figure 4-4 gives recommended r iso values for differ- ent capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n ), where g n is the circuit's noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n = +2 v/v). -1 0 1 2 3 4 5 6 -15 -14 -13 -12 -11 -10 - 9 -8 -7 -6 -5 time (1 ms/div) input, output voltage (v) v dd = 5.0v g = +2 v/v v in v out r in v ss minimum expected v in () ? 2 ma ------------------------------------------------------------------------------------- - r in maximum expected v in () v dd ? 2 ma ---------------------------------------------------------------------------------------- v in r in v out ? + mcp627x v in r iso v out c l ? + mcp627x
mcp6271/2/3/4/5 ds21810d-page 12 ? 2004 microchip technology inc. figure 4-4: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double-check the resulting frequency response peaking and step response overshoot. modify r iso 's value until the response is reasonable. bench evaluation and simula- tions with the mcp6271/2/3/4/5 spice macro model are helpful. 4.4 mcp6273/5 chip select (cs ) the mcp6273 and MCP6275 are single and dual op amps with chip select (cs ), respectively. when cs is pulled high, the supply current drops to 0.7 a (typ.) and flows through the cs pin to v ss . when this hap- pens, the amplifier output is put into a high-impedance state. by pulling cs low, the amplifier is enabled. if the cs pin is left floating, the amplifier may not operate properly. figure 1-1 shows the output voltage and supply current response to a cs pulse. 4.5 cascaded dual op amps (MCP6275) the MCP6275 is a dual op amp with chip select (cs ). the chip select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). this pin is available because the output of op amp a connects to the non-inverting input of op amp b, as shown in figure 4-5. the chip select input, which can be connected to a microcontroller i/o line, puts the device in low-power mode. refer to section 4.4 ?mcp6273/5 chip select (cs )? . figure 4-5: cascaded gain amplifier. the output of op amp a is loaded by the input imped- ance of op amp b, which is typically 10 13 ? ?? 6pf, as specified in the dc specification table (refer to section 4.3 ?capacitive loads? for further details regarding capacitive loads). the common mode input range of these op amps is specified in the data sheet as v ss ? 300 mv and v dd + 300 mv. however, since the output of op amp a is limited to v ol and v oh (20 mv from the rails with a 10 k ? load), the non-inverting input range of op amp b is limited to the common mode input range of v ss + 20 mv and v dd ?20mv. 4.6 supply bypass with this family of operational amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good, high-frequency performance. it also needs a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with other analog parts. 4.7 pcb surface leakage in applications where low input bias current is critical, printed circuit board (pcb) surface-leakage effects need to be considered. surface leakage is caused by humidity, dust or other contamination on the board. under low humidity conditions, a typical resistance between nearby traces is 10 12 ? . a 5v difference would cause 5 pa of current to flow. this is greater than the mcp6271/2/3/4/5 family?s bias current at 25c (1 pa, typ.). the easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). the guard ring is biased at the same voltage as the sensitive pin. an example of this type of layout is illustrated in figure 4-6. 10 100 1,000 10 100 1,000 10,000 normalized load capacitance; c l / g n (pf) recommended r iso ( : ) g n = 1 v/v g n = 2 v/v g n t 4 v/v a b cs 2 3 5 6 7 v ina + v outb MCP6275 1 v ina ? v outa /v inb + v inb ?
? 2004 microchip technology inc. ds21810d-page 13 mcp6271/2/3/4/5 figure 4-6: example guard ring layout for inverting gain. 1. for inverting gain and transimpedance amplifiers (convert current to voltage, such as photo detectors): a. connect the guard ring to the non-inverting input pin (v in +). this biases the guard ring to the same reference voltage as the op amp (e.g., v dd /2 or ground). b. connect the inverting pin (v in ?) to the input with a wire that does not touch the pcb surface. 2. non-inverting gain and unity-gain buffer: a. connect the non-inverting pin (v in +) to the input with a wire that does not touch the pcb surface. b. connect the guard ring to the inverting input pin (v in ?). this biases the guard ring to the common mode input voltage. 4.8 application circuits 4.8.1 active full-wave rectifier the mcp6271/2/3/4/5 family of amplifiers can be used in applications such as an active full-wave rectifier or an absolute value circuit, as shown in figure 4-7. the amplifier and feedback loops in this active voltage rectifier circuit eliminate the diode drop problem that exists in a passive voltage rectifier. this circuit behaves as a follower (the output follows the input) as long as the input signal is more positive than the reference voltage. if the input signal is more negative than the reference voltage, however, the circuit behaves as an inverting amplifier. therefore, the output voltage will always be above the reference voltage, regardless of the input signal. figure 4-7: active full-wave rectifier. the design equations give a gain of 1 from v in to v out , and produce rail-to-rail outputs. guard ring v ss v in ?v in + ? + ? + v in v out v ref v ref r 1 r 3 r 4 r 5 r 2 op amp a op amp b d 1 d 2 v ref v ref time time input output r 5 r 2 r 4 2 r 3 ------------ = r 1 r 2 r 3 == 1/2 mcp6272 1/2 mcp6272 r 4 r 3 < 1 v d 1 v ref v ss ? --------------------------- - ? ?? ??
mcp6271/2/3/4/5 ds21810d-page 14 ? 2004 microchip technology inc. 4.8.2 lossy non-inverting integrator the non-inverting integrator shown in figure 4-8 is easy to build. it saves one op amp over the typical miller integrator plus inverting amplifier configuration. the phase accuracy of this integrator depends on the matching of the input and feedback resistors, and the capacitor?s time constants. r f is used to provide feedback at frequencies << 1/(2 r 1 c 1 ) and makes this a lossy integrator (it has infinite gain at dc). figure 4-8: non-inverting integrator. 4.8.3 cascaded op amp applications the MCP6275 provides the flexibility of low-power mode for dual op amps in an 8-pin package. the MCP6275 eliminates the added cost and space in a battery-powered application by using two single op amps with chip select (cs ) lines or a 10-pin device with one cs line for both op amps. since the two op amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. however, there are several applications where this op amp configuration with a cs line becomes suitable. the circuits below show possible applications for this device. 4.8.3.1 load isolation with the cascaded op amp configuration, op amp b can be used to isolate the load from op amp a. in applica- tions where op amp a is driving capacitive or low resis- tive loads in the feedback loop (such as an integrator or filter circuit) the op amp may not have sufficient source current to drive the load. in this case, op amp b can be used as a buffer. figure 4-9: isolating the load with a buffer. 4.8.3.2 cascaded gain figure 4-10 shows a cascaded gain circuit configura- tion with chip select . op amps a and b are configured in a non-inverting amplifier configuration. in this config- uration, it is important to note that the input offset voltage of op amp a is amplified by the gain of op amp a and b, as shown below: therefore, it is recommended that you set most of the gain with op amp a and use op amp b with relatively small gain (e.g., a unity-gain buffer). + _ mcp6271 c 1 c 2 r 1 r 2 v in v out r f r 1 c 1 r 2 r f || () c 2 = a b MCP6275 cs v outb load v out v in g a g b v osa g a g b v osb g b + + = where: g a = op amp a gain g b = op amp b gain v osa = op amp a input offset voltage v osb = op amp b input offset voltage
? 2004 microchip technology inc. ds21810d-page 15 mcp6271/2/3/4/5 figure 4-10: cascaded gain circuit configuration. 4.8.3.3 difference amplifier figure 4-11 shows op amp a configured as a difference amplifier with chip select . in this configuration, it is recommended that well-matched resistors (e.g., 0.1%) be used to increase the common mode rejection ratio (cmrr). op amp b can be used to provide additional gain and isolate the load from the difference amplifier. figure 4-11: difference amplifier circuit. 4.8.3.4 inverting integrator with active compensation and c hip select figure 4-12 uses an active compensator (op amp b) to compensate for the non-ideal op amp characteristics introduced at higher frequencies. this circuit uses op amp b as a unity-gain buffer to isolate the integration capacitor c 1 from op amp a and drives the capacitor with a low-impedance source. since both op amps are matched very well, they provide a high-quality integrator. figure 4-12: integrator circuit with active compensation. 4.8.3.5 second-order mfb with an extra pole-zero pair figure 4-13 is a second-order multiple feedback low- pass filter with chip select . use the filterlab ? software from microchip to determine the r and c values for op amp a?s second-order filter. op amp b can be used to add a pole-zero pair using c 3 , r 6 and r 7 . figure 4-13: second-order multiple feedback low-pass filter with an extra pole- zero pair. a b cs r 4 r 3 r 2 r 1 v in v out MCP6275 a b cs r 2 r 1 v in2 v in1 r 2 r 1 v out r 4 r 3 MCP6275 a cs b v in v out r 1 c 1 MCP6275 a b cs r 1 c 1 r 5 v in v out c 2 r 4 r 3 r 2 r 6 c 3 MCP6275 r 7
mcp6271/2/3/4/5 ds21810d-page 16 ? 2004 microchip technology inc. 4.8.3.6 second-order sallen-key with an extra pole-zero pair figure 4-14 is a second-order sallen-key low-pass filter with chip select . use the filterlab ? software from microchip to determine the r and c values for op amp a?s second-order filter. op amp b can be used to add a pole-zero pair using c 3 , r 5 and r 6 . figure 4-14: second-order sallen-key low-pass filter with an extra pole-zero pair and c hip select . 4.8.3.7 capacitorless second-order low-pass filter with chip select the low-pass filter shown in figure 4-15 does not require external capacitors and uses only three exter- nal resistors; the op amp?s gbwp sets the corner fre- quency. r 1 and r 2 are used to set the circuit gain. r 3 is used to set the q. to avoid gain-peaking in the frequency response, q needs to be low (lower values need to be selected for r 3 ). note that the amplifier bandwidth varies greatly over temperature and process. this configuration, however, provides a low- cost solution for applications with high bandwidth requirements. figure 4-15: capacitorless second-order low-pass filter with chip select . a b cs r 2 c 1 r 1 v in v out r 4 r 3 c 2 c 3 r 5 MCP6275 r 6 a b cs v ref v in v out r 2 r 1 r 3 MCP6275
? 2004 microchip technology inc. ds21810d-page 17 mcp6271/2/3/4/5 5.0 design tools microchip provides the basic design tools needed for the mcp6271/2/3/4/5 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp6271/2/3/4/5 op amps is available on our web site at www.microchip.com. this model is intended to be an initial design tool that works well in the op amp?s linear region of operation at room temperature. see the macro model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchip?s filterlab software is an innovative tool that simplifies analog active filter (using op amps) design. it is available free of charge from our web site at www.microchip.com. the filterlab software tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance.
mcp6271/2/3/4/5 ds21810d-page 18 ? 2004 microchip technology inc. 6.0 packaging information 6.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard marking consists of microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). for marking beyond this, certain price adders apply. please check with your microchip sales office. mcp6271 e/p256 0437 mcp6271 e/sn0437 256 8-lead msop example: xxxxxx ywwnnn 6271e 437256 5-lead sot-23 ( mcp6271 and mcp6271r ) example: xxnn cg25 device code mcp6271 cgnn mcp6271r etnn note: applies to 5-lead sot-23 6-lead sot-23 ( mcp6273 ) example: xxnn ck25
? 2004 microchip technology inc. ds21810d-page 19 mcp6271/2/3/4/5 package marking information (continued) 14-lead pdip (300 mil) (mcp6274) example: 14-lead tssop (mcp6274) example: 14-lead soic (150 mil) (mcp6274) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxx yywwnnn xxxxxx yyww nnn mcp6274 -e/p 0437256 6274 est 0437 256 xxxxxxxxxx mcp6274 esl 0437256
mcp6271/2/3/4/5 ds21810d-page 20 ? 2004 microchip technology inc. 5-lead plastic small outline transistor (ot) (sot-23) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 5 5 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 p d b n e e1 l c a2 a a1 p1 exceed .005" (0.127mm) per side. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not notes: eiaj equivalent: sc-74a drawing no. c04-091 *controlling parameter
? 2004 microchip technology inc. ds21810d-page 21 mcp6271/2/3/4/5 6-lead plastic small outline transistor (ch) (sot-23) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 6 6 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 d b n e e1 l c a2 a a1 p1 exceed .005" (0.127mm) per side. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not notes: jeita (formerly eiaj) equivalent: sc-74a drawing no. c04-120 *controlling parameter
mcp6271/2/3/4/5 ds21810d-page 22 ? 2004 microchip technology inc. 8-lead plastic micro small outline package (ms) (msop) d a a1 l c (f) a2 e1 e p b n 1 2 5 5 - - dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 ref f footprint (reference) exceed .010" (0.254mm) per side. notes: drawing no. c04-111 *controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness c b .003 .009 .006 .012 dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .030 .193 typ. .033 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.23 0.40 8 millimeters* 0.65 bsc 0.85 3.00 bsc 3.00 bsc 0.60 4.90 bsc .043 .031 .037 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 -- - 15 5 - 15 5 - jedec equivalent: mo-187 0 - 8 5 5 - - 15 15 - - - -
? 2004 microchip technology inc. ds21810d-page 23 mcp6271/2/3/4/5 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
mcp6271/2/3/4/5 ds21810d-page 24 ? 2004 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2004 microchip technology inc. ds21810d-page 25 mcp6271/2/3/4/5 14-lead plastic dual in-line (p) ? 300 mil (pdip) e1 n d 1 2 eb e c a a1 b b1 l a2 p units inches* millimeters dimension limits min nom max min nom max number of pins n 14 14 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .740 .750 .760 18.80 19.05 19.30 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 5 10 15 5 10 15 mold draft angle bottom * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-005 significant characteristic
mcp6271/2/3/4/5 ds21810d-page 26 ? 2004 microchip technology inc. 14-lead plastic small outline (sl) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-065 significant characteristic
? 2004 microchip technology inc. ds21810d-page 27 mcp6271/2/3/4/5 14-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 8 4 0 8 4 0 foot angle 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b1 lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters* inches units l c 2 1 d n b p e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-087 significant characteristic
mcp6271/2/3/4/5 ds21810d-page 28 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21810d-page 29 mcp6271/2/3/4/5 appendix a: revision history revision a (june 2003) original data sheet release. revision b (october 2003) revision c (june 2004) revision d (december 2004) the following is the list of modifications: 1. added sot-23-5 packages for the mcp6271 and mcp6271r single op amps. 2. added sot-23-6 packages for the mcp6273 single op amp. 3. added section 3.0 ?pin descriptions? . 4. corrected application circuits ( section 4.8 ?application circuits? ). 5. added sot-23-5 and sot-23-6 packages and corrected package marking information ( section 6.0 ?packaging information? ). 6. added appendix a: revision history.
mcp6271/2/3/4/5 ds21810d-page 30 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21810d-page 31 mcp6271/2/3/4/5 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support part no. x /xx package temperature range device device: mcp6271: single op amp mcp6271t: single op amp (tape and reel) (soic, msop, sot-23-5) mcp6271rt: single op amp (tape and reel) (sot-23-5) mcp6272: dual op amp mcp6272t: dual op amp (tape and reel) (soic, msop) mcp6273: single op amp with chip select mcp6273t: single op amp with chip select (tape and reel) (soic, msop, sot-23-6) mcp6274: quad op amp mcp6274t: quad op amp (tape and reel) (soic, tssop) MCP6275: dual op amp with chip select MCP6275t: dual op amp with chip select (tape and reel) (soic, msop) temperature range: e = -40c to +125c package: ot = plastic small outline transistor (sot-23), 5-lead (mcp6271, mcp6271r) ch = plastic small outline transistor (sot-23), 6-lead (mcp6273) ms = plastic msop, 8-lead p = plastic dip (300 mil body), 8-lead, 14-lead sn = plastic soic, (150 mil body), 8-lead sl = plastic soic (150 mil body), 14-lead st = plastic tssop (4.4mm body), 14-lead examples: a) mcp6271-e/sn: extended temperature, 8ld soic package. b) mcp6271-e/ms: extended temperature, 8ld msop package. c) mcp6271-e/p: extended temperature, 8ld pdip package. d) mcp6271t-e/ot: tape and reel, extended temperature, 5ld sot-23 package. a) mcp6272-e/sn: extended temperature, 8ld soic package. b) mcp6272-e/ms: extended temperature, 8ld msop package. c) mcp6272-e/p: extended temperature, 8ld pdip package. d) mcp6272t-e/sn: tape and reel, extended temperature, 8ld soic package. a) mcp6273-e/sn: extended temperature, 8ld soic package. b) mcp6273-e/ms: extended temperature, 8ld msop package. c) mcp6273-e/p: extended temperature, 8ld pdip package. d) mcp6273t-e/ch: extended temperature, 6ld sot-23 package. a) mcp6274-e/p: extended temperature, 14ld pdip package. b) mcp6274t-e/sl: tape and reel, extended temperature, 14ld soic package. c) mcp6274-e/sl: extended temperature, 14ld soic package. d) mcp6274-e/st: extended temperature, 14ld tssop package. a) MCP6275-e/sn: extended temperature, 8ld soic package. b) MCP6275-e/ms: extended temperature, 8ld msop package. c) MCP6275-e/p: extended temperature, 8ld pdip package. d) MCP6275t-e/sn: tape and reel, extended temperature, 8ld soic package. ? data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. customer notification system register on our web site (www.microchip.com) to receive the most current information on our products.
mcp6271/2/3/4/5 ds21810d-page 32 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21810d-page 33 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mpasm, mplib, mplink, mpsim, pickit, picdem, picd em.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted wo rk, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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